1. Field of the Invention
The present invention relates to an associative memory in which data are stored, and also in which a match between stored data and data to be searched for is detected and output.
2. Description of the Prior Art
In order to make it easier to exercise operational control and to reduce power consumption, a conventional associated memory, which is disclosed in, for example, Japanese Unexamined Patent Publication No. Hei 2-192098, includes a memory circuit, a comparator and match detection signal lines. In this memory, since a match detection signal line for each word is held at an "L" level potential only during the course of a comparison process, a bit line controller is not required and there is a reduction in the consumption of power.
The associative memory, proposed by the above mentioned publication is the associative memory shown in FIG. 2 that employs the memory cell shown in FIG. 1.
In FIG. 1, showing a memory cell C in the conventional associative memory proposed in the above mentioned publication, a P channel MOS transistor (hereinafter referred to as a "PMOS") 501 and an N channel MOS transistor (hereinafter referred to as an "NMOS") 503 constitute a first inverter, and a PMOS 502 and an NMOS 504 constitute a second inverter. The first and the second inverters are connected together in a cross-strapped manner (i.e., their input terminals and output terminals are alternately connected) to constitute a flop-flop. An NMOS 505 and an NMOS 506 are connected between the common connection points of the first and the second inverters and paired complementary bit lines BLT and BLB, and the gates of the NMOS 505 and the NMOS 506 are connected to a word line WL so as to constitute a memory circuit 511. An NMOS 507 and an NMOS 509, and an NMOS 508 and an NMOS 510 are connected in series between a data match signal line ML and a match detection control signal line MCL, the gates of an NMOS 509 and an NMOS 510 being connected to the common connection points of the first and the second inverters, and the gates of the NMOS 507 and the NMOS 508 being connected to bit lines BLT and BLB, and thereby constitute a comparator 512.
FIG. 2 is a block diagram illustrating an associative memory constituted by the memory cells in FIG. 1. In FIG. 2, C11 to Cb1 denote memory cells; reference numeral 601, a memory cell array constituted by b memory cells; Di1 to Dib, input data; reference numerals 6021 to 602b, input data inverters; BLT1 and BLB1 to BLB1 and BLBb, bit line pairs; reference numeral 603, a write signal line; 604, a decoder for controlling word lines; 605, a precharge signal line for precharging data match signal lines ML to a high level; 606, a comparison signal line establishing a comparison operating cycle; 607, a discharge signal generator for discharging match detection signal lines MCL and bringing them to low level; 608, a discharge signal line; 609, precharge circuits; 610, discharge circuits; 611, sense amplifiers for amplifying signals on the data match signal lines ML; 612, output lines for the sense amplifiers 611; and 6131 to 613i, an assembly each for one word. The arrangement shown in FIG. 2 is an associative memory consisting of b bits and i words. When the comparison signal 606 goes high, a comparison of the input data Di with stored data is initiated.
The comparison operation for the associative memory in FIG. 2 will now be described while referring to a signal waveform diagram in FIG. 3, with the supposition that a data "0" is stored in the memory cell shown in FIG. 1, i.e., that the output of the first inverter, which includes the PMOS 501 and the NMOS 503, is low and the output of the second inverter, which includes the PMOS 502 and the NMOS 504, is high.
In FIG. 3, when the precharge signal line 605 is high during a period in which the clock for cycle A is high (H), the precharge operation for the data match signal line ML1 is halted. Since the discharge signal line 608 also goes high, the match detection control signal line MCL1 is brought low by the discharge circuit 610. Further, upon the receipt of data Di the bit line BLT1 goes high and the BLB1 goes low. At this time, since the gates of the NMOS 507 and the NMOS 509 in FIG. 1 go high and become conductive, the data match signal line ML (ML1) and the match detection control signal line MCL (MCL1) are connected together, so that the data match signal line ML1 goes low.
Following this, when the clock goes low (L), the discharge signal line 608 also goes low and the discharge operation initiated by the match detection control signal MCL1 is halted. In addition, since the precharge signal line 605 also goes low, the data match signal line ML1 is precharged to a high level by the precharge circuit 609. At this time the levels at the bit lines BLT1 and BLB1 do not change, so that the data match signal line ML1 and the match detection control signal line MCL1 are still connected and the match detection control signal line MCL1 goes high.
Next, since the precharge signal line 605 is high during a period in which the clock for cycle B is high (H), the precharge operation for the data match signal line ML1 is halted. Since the discharge signal line 608 also goes high, the match detection control signal line MCL1 is brought low by the discharge circuit 610.
Furthermore, upon receipt of the data Di the bit line BLT1 goes low and BLB1 goes high. At this time, since the gate potential of the NMOS 510 is still low, even though the gate of the NMOS 508 in FIG. 1 goes high, the data match signal line ML (ML1) and the match detection control signal MCL (MCL1) are not connected together and the data match signal line ML1 is not changed and is maintained high.
As is described above, in the comparison operation performed by the associative memory shown in FIG. 2, the data match signal line ML is shifted from high to low when the stored data and the input data do not match. In addition, since the memory cells C1k to Cbk are connected in parallel to the data match signal line MLk and the match detection control signal line MCLk, the data match signal line MLk will be brought low if there is even one bit that is not matched in the b-bit data that constitute a word.
The problems that arise with the above described associative memory will now be described.
Before data are to be read from the memory cell, the bit lines must be precharged at a high level and data on the bit lines must be erased in order to prevent damage to the data in the memory cell due to the presence of a potential difference between the bit lines. However, since precharging of the bit lines is not performed for the conventional associative memory proposed in Japanese Unexamined Patent Publication No. Hei 2-192098, data can not be read from the memory cell.
In addition, since the memory cell in the above described associative memory is constituted by b columns and i word rows, i memory cells equivalent in count to the total word count are connected to the bit lines BLT and BLB. Therefore, when the number of word lines i is large, the lengths of the bit lines BLT and BLB are increased, and the diffusion capacitances and the gate capacitances of the NMOS 505 and NMOS 507 (and the NMOS 506 and the NMOS 508) that are connected to them are also increased, with the result that the total capacitance is increased. And the increase in the capacitances of the bit lines BLT and BLB results an increase in the consumption of power and a reduction in the operational speed.
The same capacitance is provided for the data match signal line ML and the match detection control signal line MCL. And when, as the result of the comparison, it is found that the stored data and the input data do not match in one cycle, a charge/discharge is performed along the data match signal line ML and the match detection control signal line MCL. Generally, since in many cases data match is not obtained as a result of the comparison, the consumption of power is increased.